<!DOCTYPE html>

<html>
<head>
<meta charset="UTF-8">
<link href="style.css" type="text/css" rel="stylesheet">
<title>VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values </title></head>
<body>
<h1>VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.128.66.0F38.W0 4E /r</p>
<p>VRSQRT14PS xmm1 {k1}{z}, xmm2/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Computes the approximate reciprocal square roots of the packed single-precision floating-point values in xmm2/m128/m32bcst and stores the results in xmm1. Under writemask.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F38.W0 4E /r</p>
<p>VRSQRT14PS ymm1 {k1}{z}, ymm2/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Computes the approximate reciprocal square roots of the packed single-precision floating-point values in ymm2/m256/m32bcst and stores the results in ymm1. Under writemask.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F38.W0 4E /r</p>
<p>VRSQRT14PS zmm1 {k1}{z}, zmm2/m512/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Computes the approximate reciprocal square roots of the packed single-precision floating-point values in zmm2/m512/m32bcst and stores the results in zmm1. Under writemask.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>This instruction performs a SIMD computation of the approximate reciprocals of the square roots of 16 packed single-precision floating-point values in the source operand (the second operand) and stores the packed single-precision floating-point results in the destination operand (the first operand) according to the writemask. The maximum relative error for this approximation is less than 2<sup>-14</sup>.</p>
<p>EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.</p>
<p>EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1.</p>
<p>EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1.</p>
<p>The VRSQRT14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an +∞ then +ZERO value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated correctly and performs the approximation with the specified masked response. When a source value is a negative value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.</p>
<p>MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.</p>
<p>Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
<p>A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.</p>
<p><strong>Operation</strong></p>
<p><strong>VRSQRT14PS (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask* THEN</p>
<p>IF (EVEX.b = 1) AND (SRC *is memory*)</p>
<p>THEN DEST[i+31:i] (cid:197) APPROXIMATE(1.0/ SQRT(SRC[31:0]));</p>
<p>ELSE DEST[i+31:i] (cid:197) APPROXIMATE(1.0/ SQRT(SRC[i+31:i]));</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<h3>Table 5-25. VRSQRT14PS Special Cases</h3>
<table>
<tr>
<th>Input value</th>
<th>Result value</th>
<th>Comments</th></tr>
<tr>
<td>Any denormal</td>
<td>Normal</td>
<td>Cannot generate overflow</td></tr>
<tr>
<td>X = 2<sup>-2n</sup></td>
<td>2<sup>n</sup></td>
<td></td></tr>
<tr>
<td>X &lt; 0</td>
<td>QNaN_Indefinite</td>
<td>Including -INF</td></tr>
<tr>
<td>X = -0</td>
<td>-INF</td>
<td></td></tr>
<tr>
<td>X = +0</td>
<td>+INF</td>
<td></td></tr>
<tr>
<td>X = +INF</td>
<td>+0</td>
<td></td></tr></table>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VRSQRT14PS __m512 _mm512_rsqrt14_ps( __m512 a);</p>
<p>VRSQRT14PS __m512 _mm512_mask_rsqrt14_ps(__m512 s, __mmask16 k, __m512 a);</p>
<p>VRSQRT14PS __m512 _mm512_maskz_rsqrt14_ps( __mmask16 k, __m512 a);</p>
<p>VRSQRT14PS __m256 _mm256_rsqrt14_ps( __m256 a);</p>
<p>VRSQRT14PS __m256 _mm256_mask_rsqrt14_ps(__m256 s, __mmask8 k, __m256 a);</p>
<p>VRSQRT14PS __m256 _mm256_maskz_rsqrt14_ps( __mmask8 k, __m256 a);</p>
<p>VRSQRT14PS __m128 _mm_rsqrt14_ps( __m128 a);</p>
<p>VRSQRT14PS __m128 _mm_mask_rsqrt14_ps(__m128 s, __mmask8 k, __m128 a);</p>
<p>VRSQRT14PS __m128 _mm_maskz_rsqrt14_ps( __mmask8 k, __m128 a);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>See Exceptions Type 4.</p></body></html>